The reset port is used in an FPGA to return the registers and block RAM connected to the reset port to an initial value any time the reset signal is applied. Typically the most important aspect of RTL configuration is selecting the reset behavior.
The presence and behavior of the RTL reset port is controlled using the
config_rtl command, as shown in the following figure. You
can access this command by selecting the menu command.
The reset settings include the ability to set the polarity of the reset and whether the reset is synchronous or asynchronous but more importantly it controls, through the reset option, which registers are reset when the reset signal is applied.
config_rtlconfiguration. This is required by the AXI4 standard.
The reset option has four settings:
- No reset is added to the design.
- This is the default and ensures all control registers are reset. Control registers are those used in state machines and to generate I/O protocol signals. This setting ensures the design can immediately start its operation state.
- This option adds a reset to control registers (as in the control setting) plus any registers or memories derived from static and global variables in the C/C++ code. This setting ensures static and global variable initialized in the C/C++ code are reset to their initialized value after the reset is applied.
- This adds a reset to all registers and memories in the design.
Finer grain control over reset is provided through the RESET pragma or directive.
Static and global variables can have a reset added through the RESET directive.
Variables can also be removed from those being reset by using the RESET directive’s
alloptions to consider the effect on resetting arrays as discussed in Initializing and Resetting Arrays.