Examples of Disaggregation - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
Release Date
2021-12-15
Version
2021.2 English

Disaggregate AXIS Interface

This is an example of the DISAGGREGATE pragma or directive for an axis interface. The example is available in the Vitis HLS Introductory Examples.

Table 1. Disaggregated Struct on AXIS Interface
HLS Source Code Synthesized IP Module
#define N 10

struct A {
  char c;
  int i;
};

void dut(A in[N], A out[N]) {
#pragma HLS interface axis port=in
#pragma HLS interface axis port=out
#pragma HLS disaggregate variable=in
#pragma HLS disaggregate variable=out
  int sum = 0;
  for (unsigned i=0; i<N; i++) {
    out[i].c = in[i].c;
    out[i].i = in[i].i;
  }
} 
module dut (
ap_local_block,
ap_local_deadlock,
ap_clk,
ap_rst_n,
ap_start,
ap_done,
ap_idle,
ap_ready,
in_c_TVALID,
in_i_TVALID,
out_c_TREADY,
out_i_TREADY,
in_c_TDATA,
in_c_TREADY,
in_i_TDATA,
in_i_TREADY,
out_c_TDATA,
out_c_TVALID,
out_i_TDATA,
out_i_TVALID
);

In the above disaggregation example, the struct arguments in and out are mapped to AXIS interfaces, and then disaggregated. This results in Vitis HLS creating two AXI streams for each argument: in_c, in_i, out_c and out_i. Each member of the struct A becomes a separate stream.

The RTL interface of the generated module is shown on the right above where the member elements c and i are individual AXI stream ports, each with its own TVALID, TREADY and TDATA signals.

Vitis HLS will issue the following messages in the log file:
INFO: [HLS 214-210] Disaggregating variable 'in' (example.cpp:19:0)
INFO: [HLS 214-210] Disaggregating variable 'out' (example.cpp:19:0)

Disaggregate HLS::STREAM

This is an example of the DISAGGREGATE pragma or directive when used with the hls::stream type. The example is available in the Vitis HLS Introductory Examples.

Table 2. Disaggregated Struct of HLS::STREAM
HLS Source Code Synthesized IP Module
#define N 1024

struct A {,
  hls::stream<int> s_in;
  long arr[N];
};

long dut(struct A &d) {
  long sum = 0;
  while(!d.s_in.empty())
    sum += d.s_in.read();
  for (unsigned i=0; i<N; i++)
    sum += d.arr[i]; 
  return sum;
}
module dut (
ap_local_block,
ap_local_deadlock,
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
d_s_in_dout,
d_s_in_empty_n,
d_s_in_read,
d_arr_ce0, 
d_arr_q0,
ap_return
);

Using an hls::stream object inside a structure that is used in the interface will cause the struct port to be automatically disaggregated by the Vitis HLS compiler. As shown in the above example, the generated RTL interface will contain separate RTL ports for the hls::stream object s_in (named d_s_in_*) and separate RTL ports for the array arr (named d_arr_*).

Vitis HLS will issue the following messages in the log file:
INFO: [HLS 214-210] Disaggregating variable 'd'
INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'd_s_in' with compact=bit mode in 32-bits