Global Variables - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
Release Date
2021-12-15
Version
2021.2 English

Global variables can be freely used in the code and are fully synthesizable. By default, global variables are not exposed as ports on the RTL interface.

The following code example shows the default synthesis behavior of global variables. It uses three global variables. Although this example uses arrays, Vitis™ HLS supports all types of global variables.

  • Values are read from array Ain.
  • Array Aint is used to transform and pass values from Ain to Aout.
  • The outputs are written to array Aout.
    din_t Ain[N];
    din_t Aint[N];
    dout_t Aout[N/2];
    
    void types_global(din1_t idx) {
     int i,lidx;
    
      // Move elements in the input array
     for (i=0; i<N; ++i) { 
     lidx=i;
     if(lidx+idx>N-1)
     lidx=i-N;
     Aint[lidx] = Ain[lidx+idx] + Ain[lidx];
     }
    
     // Sum to half the elements
     for (i=0; i<(N/2); i++) { 
     Aout[i] = (Aint[i] + Aint[i+1])/2;
     }
    
    }
    

By default, after synthesis, the only port on the RTL design is port idx. Global variables are not exposed as RTL ports by default. In the default case:

  • Array Ain is an internal RAM that is read from.
  • Array Aout is an internal RAM that is written to.