When synthesis completes, the syn folder is created inside the solution folder. This folder contains the following elements:
- The verilog and vhdl folders contain the output RTL files.
- The top-level file has the same name as the top-level function for synthesis.
- There is one RTL file created for each sub-function that has not been inlined into a higher level function.
- There could be additional RTL files to implement sub-blocks of the RTL hierarchy, such as block RAM, and pipelined multipliers.
- The report folder contains a report file for the top-level function and one for every sub-function that has not been in-lined into a higher level function by Vitis HLS. The report for the top-level function provides details on the entire design.
Important: You should not use the RTL files generated in the syn/verilog or syn/vhdl folder for synthesis in the Vivado tool. You should instead use the packaged output files for use with the Vitis application acceleration development flow, or the Vivado Design Suite as described in Exporting the RTL Design. In cases where Vitis HLS uses Xilinx IP in the generated RTL code, such as with floating point designs, the verilog and vhdl folders contain a script to create that IP during RTL synthesis by the Xilinx tools. If you use the files in the syn/verilog or syn/vhdl folder directly for RTL synthesis, you must also correctly use any script files present in those folders. If the packaged output is used, this process is performed automatically by the Xilinx tools.