After the project and solution have been created, you can configure default settings of the Vitis HLS tool using the menu command. This command opens the Solution Settings dialog box for the currently active solution.
The Solutions Setting dialog box provides access to the following settings:
- Displays the Configuration Settings page for the current solution, listing settings that generally apply to the Vitis HLS tool overall.
- Synthesis settings are initially defined when the project is created as described in Creating a New Vitis HLS Project.
- These settings control the C/RTL Co-simulation feature as described in C/RTL Co-Simulation in Vitis HLS.
- These settings affect the output generated by Vitis HLS as described in Exporting the RTL Design.
- RTL Synthesis
- These settings affect the results and reports generated by Vivado synthesis as described in Exporting the RTL Design.
- Place and Route
- These settings affect the results and reports generated by Vivado implementation as described in Exporting the RTL Design.
On the Configuration
Settings page, as displayed in the figure above, you have
access to the various configuration commands like
These commands are described in detail in Configuration Commands.
Select one of the listed configuration commands, and click the
Expand All (
+) command to expand the selected configuration command to view the
available options. You can edit the options for the selected command, or use the
Reset all (
X) command to restore the selected configuration to its default
Use the Collapse All
-) command to collapse any selected
Use the Help (
?) command to open a window that provides a text
description of the selected configuration command and all its options.
Enable the Show only non-defaults check box to only display the configuration commands that have been modified from their default values.
Click OK to confirm the settings of the various configuration commands and close the Solution Settings dialog box. Click Cancel to cancel any changes and close the dialog box.
On the Synthesis Settings page, as shown in the following figure, you have access to the various settings to drive the synthesis process, such as the target Xilinx device, the clock period and uncertainty, and the target flow for the solution.
- Specify the clock period in units of nanoseconds (ns), or as a frequency value specified with the MHz suffix (for example, 150 MHz). Refer to Specifying the Clock Frequency for more information.
- Specify the clock uncertainty used for synthesis as the clock period minus the clock uncertainty. Vitis HLS uses internal models to estimate the delay of the operations for each device. The clock uncertainty value provides a controllable margin to account for any increases in net delays due to RTL logic synthesis, place, and route. Specify as a value in ns, or as a percentage of the clock period. The default clock uncertainty is 12.5% of the clock period.
- Specify the target device (Part) for your project by clicking the Browse button (…) to open the Device Selection Dialog box to select a device or board for the solution. You can click the Search filter to reduce the number of devices listed.
- Select the Flow Target as explained in Vitis HLS Process Overview.