Design with AI Engine and HDL Blocks - 2021.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2021-10-22
Version
2021.2 English

This section discusses generating the hardware image for a design that contains AI Engine and HDL blocks. You can connect the blocks from HDL Library alongside the AI Engine blocks and still generate the hardware image as described in the Design with AI Engine and HLS Kernel Blocks. However, additionally you need to perform an extra step to generate the code for HDL blocks prior to generating the hardware image using Model Composer Hub block.

To understand more, consider the same 2D-FFT example, but now implemented using an HDL block as shown in the following figure.

Figure 1. 2D FFT using AI Engines and PL (HDL)

Here, the subsystem aie_2dfft is the AI Engine portion of the design and the hdl_2dfft subsystem is the Programmable Logic (HDL) portion of the design.

This example is available in GitHub.

As depicted in the previous figure, the design uses the System Generator Token block to generate the code for the HDL portion of the design. The following sequence should be followed for hardware image generation:
  1. Generate code for HDL blocks from System Generator token.
  2. Generate code for AI Engine blocks from the Model Composer Hub block.

The hardware image generation from the Model Composer Hub block depends on the generated HDL netlist. This necessitates the above sequence to be followed.