Design with AI Engine and HLS Kernel Blocks - 2021.2 English

Vitis Model Composer User Guide (UG1483)
Document ID
UG1483
Release Date
2021-10-22
Version
2021.2 English

This section discusses generating the hardware image for a design that contains AI Engine and HLS kernel blocks. You can connect the HLS kernel block alongside the AI Engine blocks and still generate the hardware image.

Figure 1. 2D FFT using AI Engines and PL (HLS)

Consider the design shown in the previous figure, where the HLS kernel block is connected between two AIE kernel blocks. This example reads in complex data from the MRI signal, performs a 2D FFT algorithm on this data using AIE and HLS blocks and displays the corresponding image of the brain at output. As depicted in the figure, the AI Engine kernels are joined to form an AI Engine subsystem which will be targeted to the AI Engine portion of the Versal hardware, and the HLS kernel block is targeted to the PL portion. This example is available in GitHub.

To generate a hardware image and validate the design on hardware, Vitis Model Composer provides an option in the Model Composer Hub block. You need to enable the Generate Hardware Image check box from the Model Composer hub block using the following steps:
  1. On the Code Generation tab within the Hub block, specify the Target as AI Engines.
  2. Select the Create testbench check box.
  3. On the Hardware tab, select Specify Platform from the drop down menu and specify the full path of the valid platform.
    Note: Code for the hardware validation flow will not be generated unless a valid platform has been specified in the Hardware tab of the Model Composer Hub block.
  4. Go back to the Code Generation tab and select the Generate Hardware Image check box.
  5. Click Apply and then Generate.
Figure 2. Generate Hardware Image
Note: You can optionally select the Run AIE Simulation check box. This is not necessary for Hardware Validation flow, but selecting this option allows you to verify the simulation results of your design using AIE Simulator.

At the end of successful code generation, with Generate Hardware Image selected in the hub block, BOOT.BIN will be generated. You will see the following in the Simulink progress window.

INFO]: Bootimage geneated successfully
...
...
**************************************************
XMC_RUNHW_INFO: Finished running run_hw.sh
**************************************************
SUCCESS

This boot image can then be run on hardware to validate simulation outputs with the results from hardware. For more information on running BOOT.BIN on hardware see Running BOOT.BIN on Hardware.