Generating HDL Code - 2021.2 English

Vitis Model Composer User Guide (UG1483)

Document ID

UG1483

Release Date

2021-10-22

Version

2021.2 English

Open the System Generator block and specify the following options:

For Part select Versal AI Core Series > xcvc1902 → -2MP-e-S → vsva2197.
Select IP Catalog from the list of Compilation targets.
Click Settings next to the IP Catalog selection box to launch IP Catalog Settings dialog and specify Xilinx.com in the Vendor edit box. Click OK.
Select Verilog from the drop-down menu under Hardware description.
Under Target directory, specify ./netlist.
Note: Target directory must be ./netlist for Hardware Validation flow. This limitation will be relaxed in future releases.

The code generation for the AI Engine subsystem and the hardware validation flow remains the same as explained in Design with AI Engine and HLS Kernel Blocks.