The hardware validation flow for AI Engines in Vitis Model Composer provides a
methodology to verify AI Engine-based applications on Xilinx hardware (Versal devices).
Vitis Model Composer provides a set of blocks in
the Simulink library browser that make it easy to develop applications for Xilinx
devices by integrating HDL/HLS blocks for the Programmable Logic (PL) and AI Engine
blocks for the AI Engine array. Vitis Model Composer
can be used to create complex systems targeting the PL and AI Engine array at the same
time. The complete system can be simulated in Simulink followed by code generation (HDL
for the PL and C++ graph for the AI Engine array). Vitis Model Composer also provides the option to generate a hardware
image (BOOT.BIN) targeting a specific platform for the Simulink model. This hardware
image can then be run on a board to verify whether the results from hardware match with
the simulation outputs.
Important:
Vitis Model Composer supports integration of
blocks from the AI Engine library with the HDL library to generate a hardware image.
However, to integrate with HLS C/C++ code, you should import using HLS Kernel block,
and not the blocks from HLS library.