Model Composer Hub - 2021.2 English

Vitis Model Composer User Guide (UG1483)

Document ID: UG1483
Release Date: 2021-10-22
Version: 2021.2 English

Control implementation of the model.

Description

The Model Composer Hub block controls the behavior of the Vitis Model Composer tool.

You can specify the targeted design flow for the generated output, the directory path for the output, and the desired device and design clock frequency using the following tabs.

The Code Generation tab provides options to select the output flow through Subsystem name, Code directory, Target, and Create testbench options.
The Hardware tab helps with device or board selection. You can specify clock frequency and throughput factor for the model.
The Feedback tab is used to provide feedback to the tool developers, and suggestions to improve the tool.

Library

Tools

Data Type Support

Data type support is not applicable to the Model Composer Hub block.

Parameters

Figure 1. Model Composer Block Parameters

Code Generation tab

Subsystem name

Enter a subsystem name that contains only Model Composer blocks.

Code directory

Enter the output directory name with the complete path, or use the Browse button to provide a path.

Target

Target settings are shown in the following table.

Table 1. Target Settings
Setting	Description
IP Catalog	Select IP Catalog to export the design to the Vivado IP Catalog. After C/C++ code generation, Vitis High-Level Synthesis (HLS) is invoked to synthesize the C code and create a project that can be exported as an IP to the Vivado IP Catalog.
System Generator	Select System Generator to export the design to HDL blockset. After C/C++ code generation, Vitis High-Level Synthesis (HLS) is invoked to synthesize the C code and create an RTL solution that can be used as a Vitis HLS block in a HDL model.
HLS C++ code	Select HLS C++ code to compile the design model into C++ code.
AI Engines	This is the default selection which allows you to generate the dataflow graph code and verify it using the AIE Simulation.

Compiler options

When enabled, this option provides control over compiler debug options, execution target options etc.

Note: This option is only available when the target is AI Engines.

Create testbench

When enabled, Model Composer generates the test vectors while generating the code.

Run AIE Simulation

This option is only available if Create testbench is selected. When enabled, it runs the AIE simulation after code generation.

Note: This option is only available when the target is AI Engines.

Collect profiling statistics and enable 'printf' for debugging

When enabled, this option allows profiling data to be collected for analysis.

Note: This option is only available when the target is AI Engines.

Collect data for Vitis Analyzer

When enabled, this option provides a summary of the simulation results which can be viewed in the Vitis Analyzer.

Note: This option is only available when the target is AI Engines.

Open Vitis Analyzer

Click to invoke the Vitis Analyzer tool.

Note: This option is only enabled after AIE Simulation has been ran at least once after enabling the Collect Data for Vitis Analyzer option.

Plot AIE Simulation output and estimate throughput

When enabled, this option logs simulation data and allows visualization of the output of an AI Engine subsystem.

Note: This option is only available when the target is AI Engines.

Generate Hardware Image

When this option is enabled, the tool generates a boot image which can be programmed on a Versal device.

Note: This option is only available to select when a valid platform is specified in the Hardware tab.

Create and run testbench

If selected, Model Composer runs simulation and generates test vectors while generating code.

Important: This option is only available when the target is set to IP Catalog, System Generator, or HLS C++ code.

Testbench stack size

This parameter prompts you to enter a larger stack size.

When Create and run testbench is enabled, the Testbench stack size option specifies the size of the testbench stack frame during C simulation (CSIM). Occasionally, the default stack frame size of 10 MB allocated for execution of the testbench may be insufficient to run the test, due to large arrays allocated on the stack and/or deep nesting of sub-systems. Typically when this happens, the test would fail with a segmentation fault and an associated error message. In such a case you may opt to increase the size of the stack frame and rerun the test.

Hardware tab

Platform: By default no platform is specified. Selecting Specify Platform from the dropdown, allows you to specify a valid hardware platform by browsing to a particular location. It is not mandatory to specify a platform for generating the data-flow graph code.

The following options are available only when the target is set to IP Catalog, System Generator, or HLS C++ code:

Project device

Specifies the current target part or board platform for the Model Composer model.

Clicking the browse button (…) next to Project device displays the Device Chooser dialog box, which allows you to select the board or part to which your design is targeted. Vitis Model Composer obtains board and device data from the Vivado database.

FPGA clock frequency

Specifies the clock frequency in MHz for the Xilinx device. This frequency is passed to the downstream tool flow.

Throughput factor

Specifies the number of samples processed per clock to increase the throughput. A larger factor increases hardware resource usage. The throughput factor must be between 1 and 16.

Feedback tab: This tab requests feedback to the tool developers, and suggestions to improve the tool. It points to a weblink that opens a survey that can be completed in less than 3 minutes.