Step 1: Know the Initiation Interval (ii) of your HDL Design
A factor in setting the Output Sample Time in the AIE to HDL block is the initiation
interval (II) of the HDL subsystem. As mentioned previously, simulation in HDL
domain is cycle-accurate. An HDL design may not be ready to accept new data at every
cycle (the tready signal from the HDL design will
be set to zero when the HDL design cannot accept a new sample). For example, if an
HDL design accepts a new sample every 10th cycle, the design is said to have an II
of 10.
Step 2: Set the Parameter Output Data Type of the AIE to HDL Block
The Output Data Type parameter is limited to
32, 64, and 128 bits wide. This reflects the permissible data bit-width between AI
Engine array and PL. There are more constraints in place. For example, if the input
signal is of type int64, the output data type can
only be of type int64. If the input is of type
int16(c), then the output should be uint32. Note that if you are using an AIE Signal Spec
block to specify the PLIO width (to optimize throughput between AI Engine array and
PL), then the Output Data Type should have the same number of bits as the PLIO width
specified. In the absence of the AIE Signal Spec block, the generated code will have
a PLIO width equal to the bitwidth of the signal leaving the AI Engine subsystem or
32 bits, whichever is larger. See Figure 3.
To get the list of Output data types that are supported by the AIE to HDL block and the corresponding input data type to the block, refer to the AIE to HDL block.
Following are some examples.
| Data Type into the Block | PLIO | Output Data Type |
|---|---|---|
| int16 | 64 bits | uint64 |
| int16(c) | Not set | uint32 |
| int32 | 128 bits | ufix128 |
| int8 | Not set | uint32 |
Step 3 : Set the Parameter Output Sample Time of the AIE to HDL Block
Set the Output Sample Time to (Input Sample
Period)/(Input Size)/ii.
To understand the reason for this formula, assume ii is one (tready
is always set to one). If the input to the AIE to HDL block is a variable-size
signal of size Input Size, and the period is Input
Period (you can determine the sample period by opening the Timing Legend in Simulink), this means in
the time period Input Period, we are feeding Input
Size samples into the block. To prevent the internal buffer of the
block from overflowing, the output rate from the AIE to HDL block should be the same
as its input. The input rate is (Input Size)/(Input
Period) and the output rate is 1/(Output
Sample Time). When ii is larger than one, the output rate is
reduced to 1/(Output Sample Time)/ii.
Step 4 : Set the System Clock
Open the Clocking tab in the System Generator block.There are two parameters there, the FPGA clock period and the Simulink system period. These two numbers define the scaling factor between time in a Simulink simulation, and time in the actual hardware implementation. Set the Simulink system period to the time calculated in step 3. Here it is assumed that the HDL design is a single-rate design. To learn more about these parameters, refer to the System Generator block.
Following is an example for connecting an AIE Kernel to an AIE to HDL block. The output datatype bit width should match the size of PLIO. Note that in absence of the PLIO block, the PLIO width is set to the larger signal bitwidth or 32-bit. With the PLIO block, you can specify a PLIO larger than 32-bits to improve throughput.
