Setting the HDL-AIE Block - 2021.2 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2021-10-22
Version
2021.2 English

Step 1: Set the Output Data Type

The Output Data Type should be set to the data type that the consuming AI Engine block accepts. Note that the size you set for the PLIO should match the input bitwidth to the HDL to AIE block while the output data type of the HDL to AIE block should match the input data type of the consuming AIE block. See Figure 1.

To get list of Output data types that are supported by the HDL to AIE block and the corresponding input data type to the block, refer to HDL to AIE.

The following table shows the Output Data Types that are supported by the HDL to AIE block and the corresponding Input data types to the block.

Step 2: Set the Output Frame Size

Assume that the consuming AIE block has a window input size of P, or it has a stream input that needs to read P samples to unblock (for example a readincr_v4 requires four input samples to unblock). Set samples per output frame to P.

Step 3: Set the Output Sample Time

Set the Output Sample Time to:

Step 4: Set the Tready Sample Time

The Tready Sample Time should be the same as the HDL design sample time.

The following figure shows an example for connecting the HDL to AIE block to an AIE Kernel with input window. Matching color boxes have the same values. Note that in the absence of a PLIO block the PLIO width is set to the larger of the signal bit width out of the HDL-AIE block and 32.

Figure 1. HDL-AIE to AIE Kernel Connection