In this lab, you will learn how to use the Vitis Model Composer HDL library to specify a design in Simulink® and synthesize the design into an FPGA. This tutorial uses a standard FIR filter and demonstrates how Vitis Model Composer provides you the design options that allow you to control the fidelity of the final FPGA hardware.
Objectives
After completing this lab, you will be able to:
- Capture your design using the Vitis Model Composer HDL Blocksets.
- Capture your designs in either complex or discrete Blocksets.
- Synthesize your designs in an FPGA using the Vivado® Design Environment.
Procedure
This lab has four primary parts:
- Step 1
- Review an existing Simulink design using the Xilinx® FIR Compiler block, and review the final gate level results in Vivado.
- Step 2
- Use over-sampling to create a more efficient design.
- Step 3
- Design the same filter using discrete blockset parts.
- Step 4
- Understand how to work with Data Types such as Floating-point and Fixed-point.