Part 2: Designing with Fixed-Point Data Types - 2021.2 English

Vitis Model Composer Tutorial (UG1498)
Document ID
UG1498
Release Date
2021-11-29
Version
2021.2 English
In this part you will re-implement the design from Part 1: Designing with Floating-Point Data Types using fixed-point data types, and compare this new design with the original design. This exercise will demonstrate the advantages and disadvantages of using fixed-point types and how Vitis Model Composer allows you to easily compare the designs, allowing you to make trade-offs between accuracy and resources within the Simulink environment before committing to an FPGA implementation.
  1. At the command prompt, type open Lab1_4_2.slx to open the design shown in the following figure.

  2. In the MATLAB Command Window enter: 
    MyCoeffs = xlfda_numerator('FDATool')
  3. Double-click the instance Gateway In2 to confirm the data is being sampled as 16-bit fixed-point value.
  4. Click Cancel to exit the Properties Editor.
  5. Click the Run simulation button to simulate the design and confirm instance Spectrum Analyzer HDL Fixed shows the filtered output.

    As you will see if you examine the output of instance FIR-Fixed-Point (shown in the previous figure) Vitis Model Composer has automatically propagated the input data type through the filter and determined the output must be 43-bit (with 28 binary bits) to maintain the resolution of the signal.

    This is based on the bit-growth through the filter and the fact that the filter coefficients (constants in instance FIR-Fixed-Point) are 16-bit.

  6. In the MATLAB Command Window, enter sum(abs(MyCoeffs)) to determine the absolute maximum gain using the current coefficients.

    Taking into account the positive and negative values of the coefficients the maximum gain possible is 1.2070 and the output signal should only ever be slightly smaller in magnitude than the input signal, which is a 16-bit signal. There is no need to have 15 bits (43-28) of data above the binary point.

    You will now use the Reinterpret and Convert blocks to manipulate the fixed-point data to be no greater than the width required for an accurate result and produce the most hardware efficient design.

  7. Right-click with the mouse anywhere in the canvas and select Xilinx BlockAdd.
  8. In the Add Block entry box, type Reinterpret.
  9. Double-click the Reinterpret component to add it to the design.
  10. Repeat the previous three steps for these components:
    1. Convert
    2. Scope
  11. In the design, select the Gateway Out2 instance.
    1. Right-click and use Copy and Paste to create a new instance of the Gateway Out block.
    2. Paste twice again to create two more instances of the Gateway Out (for a total of three new instances).
  12. Double-click the Scope component.
    1. In the Scope properties dialog box, select File > Number of Inputs > 3.
    2. Select View > Configuration Properties and confirm that the Number of input ports is 3.

    3. Click OK to close the Configuration Properties dialog box.
    4. Select File > Close to close the Scope properties dialog box.
  13. Connect the blocks as shown in the next figure.
  14. Rename the signal names into the scope as shown in the following figure: Convert, Reinterpret and Growth.

    To rename a signal, click the existing name label and edit the text, or if there is no text double-click the wire and type the name.



  15. Click the Run simulation button to simulate the design.
  16. Double-click the Scope to examine the signals.
    Tip: You might need to zoom in and adjust the scale in View > Configuration Properties to view the signals in detail.


    The Reinterpret and Convert blocks have not been configured at this point and so all three signals are identical.

    The HDL Reinterpret block forces its output to a new type without any regard for retaining the numerical value represented by the input. The block allows for unsigned data to be reinterpreted as signed data, or, conversely, for signed data to be reinterpreted as unsigned. It also allows for the reinterpretation of the data's scaling, through the repositioning of the binary point within the data.

    In this exercise you will scale the data by a factor of 2 to model the presence of additional design processing which might occur in a larger system. The Reinterpret block can also be used to scale down.

  17. Double-click the Reinterpret block to open the Properties Editor.
  18. Select Force Binary Point.
  19. Enter the value 27 in the input field Output Binary Point and click OK.

    The HDL Convert block converts each input sample to a number of a desired arithmetic type. For example, a number can be converted to a signed (two's complement) or unsigned value. It also allows the signal quantization to be truncated or rounded and the signal overflow to be wrapped, saturated, or to be flagged as an error.

    In this exercise, you will use the Convert block to reduce the size of the 43-bit word back to a 16-bit value. In this exercise the Reinterpret block has been used to model a more complex design and scaled the data by a factor of 2. You must therefore ensure the output has enough bits above the binary point to represent this increase.

  20. Double-click the Convert block to open the Properties Editor.
  21. In the Fixed-Point Precision section, enter 13 for the Binary Point and click OK.
  22. Save the design.
  23. Click the Run simulation button to simulate the design.
  24. Double-click the Scope to examine the signals.
    Tip: You might need to zoom in and adjust the scale in View > Configuration Properties to view the signals in detail.

    In the following figure you can see the output from the filter (Growth) has values between plus and minus 1. The output from the Reinterpret block moves the data values to between plus and minus 2.

    In this detailed view of the waveform, the final output (Convert) shows no difference in fidelity, when compared to the reinterpret results, but uses only 16 bits.



    The final step is to synthesize this design into hardware.

  25. Double-click the System Generator token to open the Properties Editor.
  26. On the Compilation tab, ensure the Compilation target is IP catalog.
  27. On the Clocking tab, under Perform analysis select Post Synthesis and from Analyzer type menu select Resource. This option gives the resource utilization details after completion.
    Note: In order to see accurate results from Resource Analyzer Window it is recommended to specify a new target directory rather than use the current working directory.
  28. Click Generate to compile the design into a hardware description. After completion, it generates the resource utilization in Resource Analyzer window as shown in the following figure.

  29. Click OK to dismiss the Compilation status dialog box.
  30. Click OK to dismiss the System Generator token.

    Notice, as compared to the results in Step 1, these results show approximately:

    • 45% more Flip-Flops
    • 20% more LUTs
    • 30% more DSP48s

    However, this design contains both the original floating-point filter and the new fixed-point version: the fixed-point version therefore uses approximately 75-50% fewer resources with the acceptable signal fidelity and design performance.

  31. Exit Vivado.
  32. Exit the Lab1_4_2.slx worksheet.