Step 2: Modeling Blocks with HDL

In this step, you will import an RTL design into Vitis Model Composer as a black box.

A black box allows the design to be imported into Vitis Model Composer even though the description is in Hardware Description Language (HDL) format.

Invoke Vitis Model Composer and from the MATLAB console, change the directory to: \HDL_Library\Lab2\HDL.
The following files are located in this directory:
- Lab2_2.slx - A Simulink model containing a black box example.
- transpose_fir.vhd - Top-level VHDL for a transpose form FIR filter. This file is the VHDL that is associated with the black box.
- mac.vhd – Multiply and adder component used to build the transpose FIR filter.
Type open Lab2_2.slx on the MATLAB command line.
Open the subsystem named Down Converter.
Open the subsystem named Transpose FIR Filter Black Box.
At this point, the subsystem contains two input ports and one output port. You will add a black box to this subsystem:
Right-click the design canvas, select Xilinx BlockAdd, and add a Black Box block to this subsystem.
A browser window opens, listing the VHDL source files that can be associated with the black box.
From this window, select the top-level VHDL file transpose_fir.vhd. This is illustrated in the following figure.

The associated configuration M-code transpose_fir_config.m opens in an Editor for modifications.
Close the Editor.
Wire the ports of the black box to the corresponding subsystem ports and save the design.
Double-click the Black Box block to open this dialog box:

The following are the fields in the dialog box:

Block configuration m-function

This specifies the name of the configuration M-function for the black box. In this example, the field contains the name of the function that was generated by the Configuration Wizard. By default, the black box uses the function the wizard produces. You can however substitute one you create yourself.

Simulation mode

There are three simulation modes:

Inactive

In this mode the black box participates in the simulation by ignoring its inputs and producing zeros. This setting is typically used when a separate simulation model is available for the black box, and the model is wired in parallel with the black box using a simulation multiplexer.

Vivado Simulator

In this mode simulation results for the black box are produced using co-simulation on the HDL associated with the black box.

External co-simulator

In this mode it is necessary to add a Questa HDL co-simulation block to the design, and to specify the name of the Questa block in the HDL co-simulator to use field. In this mode, the black box is simulated using HDL co-simulation.
Set the Simulation mode to Inactive and click OK to close the dialog box.
Move to the design top-level and run the simulation by clicking the Run simulation button , then double-click the Scope block.
Notice the black box output shown in the Output Signal scope is zero. This is expected because the black box is configured to be Inactive during simulation.
From the Simulink Editor menu, select Other Displays > Signals & Ports > Port Data Types to display the port types for the black box.
Compile the model (Ctrl-D) to ensure the port data types are up to date.
Notice that the black box port output type is UFix_26_0. This means it is unsigned, 26-bits wide, and has a binary point 0 positions to the left of the least significant bit.
Open the configuration M-function transpose_fir_config.m and change the output type from UFix_26_0 to Fix_26_12. The modified line (line 26) should read:
```
dout_port.setType('Fix_26_12');
```
Continue the following steps to edit the configuration M-function to associate an additional HDL file with the black box.

Locate line 65:

this_block.addFile('transpose_fir.vhd');

Immediately above this line, add the following:
```
this_block.addFile('mac.vhd');
```
Save the changes to the configuration M-function and close the file.
Click the design canvas and recompile the model (Ctrl-D).
Your Transpose FIR Filter Black Box subsystem should display as follows:
From the Black Box block parameter dialog box, change the Simulation mode field from Inactive to Vivado Simulator and then click OK.
Move to the top-level of the design and run the simulation.
Examine the scope output after the simulation has completed.
Notice the waveform is no longer zero. When the Simulation Mode was Inactive, the Output Signal scope displayed constant zero. Now, the Output Signal shows a sine wave as the results from the Vivado Simulation.
Right-click the Output Signal display and select Configuration Properties. In the Main tab, set Axis Scaling to the Auto setting.
You should see a display similar to that shown below.

Step 2: Modeling Blocks with HDL - 2021.2 English

Vitis Model Composer Tutorial (UG1498)