Step 3: Specifying Clock Domains - 2021.2 English

Vitis Model Composer Tutorial (UG1498)
Document ID
UG1498
Release Date
2021-11-29
Version
2021.2 English
In this step you will specify a different clock domain for each subsystem.
  1. Double-click the System Generator token to open the Properties Editor.
  2. Select the Clocking tab.
  3. Click Enable multiple clocks.
    Note: The FPGA clock period and the Simulink system period are now greyed out. This option informs Vitis Model Composer that clock rate will be specified separately for each hierarchy. It is therefore important the top level contains only subsystems and FIFOs; no other logic should be present at the top level in a multi-rate design.


  4. Click OK to close the Properties Editor.

    You will now specify a new clock rate for the CTRL block. The CTRL block will be driven from a CPU which executes at 100 MHz.

  5. Select the System Generator token.
  6. Press the Ctrl+C key or right-click to copy the token.

    You will specify a new clock rate for the CTRL block. This block will be clocked at 100 MHz and accessed using an AXI4-Lite interface.

  7. Double-click the CTRL block to navigate into the subsystem.
  8. Press the Ctrl+V key or right-click to paste a System Generator token into CTRL.
  9. Double-click the System Generator token to open the Properties Editor.
  10. Select the Clocking tab.
  11. Deselect Enable multiple clocks (this was inherited when the token was copied).
  12. Change the FPGA clock period to 1e9/100e6.
  13. Change the Simulink system period to 1/100e6.

  14. Click OK to close the Properties Editor.
  15. Double-click the Gateway In instance POWER_SCALE to open the Properties Editor.
  16. Change the Sample period to 1/100e6 to match the new frequency of this block.

    In the Implementation tab, note that the Interface is set to AXI4-Lite. This will ensure this port is implemented as a register in an AXI4-Lite interface.

  17. Click OK to close the Properties Editor.
  18. Select and copy the System Generator token.
  19. Click the Up to Parent toolbar button to return to the top level.

    You will now specify a new clock rate for the Gain Control block. The Gain Control block will be clocked at the same rate as the output from the DDC, 61.44 MHz.

  20. Double-click the Gain Control block to navigate into the subsystem.
  21. Press the Ctrl+V key or right-click to paste a System Generator token into Gain Control.
  22. Double-click the System Generator token to open the Properties Editor.
  23. Select the Clocking tab.
  24. Change the FPGA clock period to 1e9/61.44e6.
  25. Change the Simulink system period to 1/61.44e6.

  26. Click OK to close the Properties Editor.

    Note that the output signals are prefixed with M_AXI_DATA_. This will ensure that each port will be implemented as an AXI4 interface, because the suffix for both signals is a valid AXI4 signal name (tvalid and tdata).

  27. Click the Up to Parent toolbar button to return to the top level.

    The DDC block uses the same clock frequency as the original design, 491 MHz, because this is the rate of the incoming data.

  28. In the top-level design, select and copy the System Generator token.
  29. Double-click the DDC block to navigate into the subsystem.
  30. Press the Ctrl+V key or right-click to paste a System Generator token into the DDC.
  31. Double-click the System Generator token to open the Properties Editor.
  32. Select the Clocking tab.
  33. Deselect Enable multiple clocks. The FPGA clock period and Simulink system period are now set to represent 491 MHz.

  34. Click OK to close the Properties Editor.
  35. Use the Up to Parent toolbar button to return to the top level.
  36. Save the design.
  37. Click the Run simulation button to simulate the design and confirm the same results as earlier.

    The design will now be implemented with three clock domains.

  38. Double-click the top-level System Generator token to open the Properties Editor.
  39. Click Generate to compile the design into a hardware description.
  40. Click Yes to dismiss the simulation warning.
  41. When generation completes, click OK to dismiss the Compilation status dialog box.
  42. Click OK to dismiss the System Generator token.
  43. Open the file \HDL_Library\Lab4\IPP_QT_MCD_0001\DDC_HB_hier\ip\hdl\lab4_1.vhd to confirm the design is using three clocks, as shown in the following. 
    entity lab4_1 is
  port (
     ctrl_clk : in std_logic;
     ddc_clk : in std_logic;
     gain_control_clk : in std_logic;