There are many clocks present in the PS subsystem which need to be added correctly into the PS Sheet for Zynq UltraScale+ MPSoC XPE. If a Vivado design with PS IP exists, then run the report power to generate a .xpe file and import it back to XPE. This method ensures that the PS clocks are set appropriately to reflect the evaluated Vivado design.
If you want to initiate XPE PS clocks from scratch, use the following guidelines to provide accurate clock information to the tool:
- Use the Zynq UltraScale+ MPSoC
Vivado IP from IP catalog as shown in the following
- Customize this IP to view all of the clocking information in the
Clock Configuration - Output Clocks tab with default clock rates already
Low and Full power interconnect clock rates are called LPD_SWITCH (LP) and TOPSW_MAIN (FP) in the clock configuration tab as shown in the following figure in green color boxes.
- The following block clocks can be generated with clock
configuration tab of Zynq UltraScale+ MPSoC IP:
- R5 Clocks:
- A53/GPU Clocks:
- CSU and PMU Clocks:
Note: The CSU value is given in the data sheet for the device but the rate is fixed. The PMU value is not in the data sheet but is the same as the CSU rate.
- Full power / Low power interconnect clocks:
Note: The FP and LP interconnect clocks can be generated using the TOPSW_MAIN and LPD_SWITCH.
- R5 Clocks:
- Customize the Zynq UltraScale+ IP and use the PLL Options
section of Clock Configuration to generate the PLL section (marked as blue boxes
in the following figure).
The corresponding blocks for PLL in XPE are shown below.
- The remaining sections for DDR memory, SERDES interface, and PSIO are all design dependent.
- After the basic setup is complete, you can manipulate the setup using the global settings box shown in Figure 1. This allows you to see the impact of turning some of the A53s or GPUs, etc. on or off.