UltraRAM support for UltraScale+ Devices - 2021.2 English

Xilinx Power Estimator User Guide (UG440)

Document ID
Release Date
2021.2 English

The UltraRAM (URAM) is a high density FPGA 288Kb memory building block. URAMs coexist with BRAMs in UltraScale+ devices. The 288 Kb blocks are cascadable to enable deeper memory implementation. The URAMs may exist with very little or no fabric resources and with no timing penalty, if pipelined appropriately.

Both of the ports share the same clock and can address all of the 4K x 72 bits. Each port can independently read from or write to the memory array. URAM supports two types of write enable schemes. The first mode is consistent with the block RAM byte write enable mode.

The second mode allows gating the data and parity byte writes separately. Multiple URAM blocks can be cascaded together to create larger memory arrays. Dedicated routing in the URAM column enables the entire column height to be connected together. This makes URAM an ideal solution for replacing external memories such as SRAM.

The URAM Sheet provides columns to enter the number and configurations of the URAMs intended to be used for the design. It also displays the resulting power for the VCCINT and VCCBRAM power rails. The Utilization shows the number of URAM blocks (URAM288) used in the target device.

Figure 1. UltraRAM Power Sheet for UltraScale+ Devices

Following are descriptions of the columns used for design entry:

Enter a name to identify the URAM or URAM module.
The Number of UltraRams in this module.
Cascade Group Size
URAM blocks support cascading to create larger memory arrays while reducing the overall power by enabling only one URAM of a cascade at a time.

Example: 20 URAM blocks with a Cascade Group Size of 4 represents 20/4 = 5 sets of cascaded URAMs of 4 blocks each. If there is no cascading, use 1 as the value of cascade group size.

The optional URAM pipeline registers are IREG_PRE (input) or REG_CAS (cascade). The default value is Cascade Group Size divided by 3. If there is no URAM cascading, only IREG_PRE can be used which corresponds to a Latency of 1.
Chooses between URAM288 (no ECC) and URAM288_with_ECC.
Sleep Rate
The percentage of time the URAM SLEEP input pin is asserted. The value of Auto is also supported for Automatic Sleep Mode.
Average Inactive Cycles
The average number of consecutive inactive cycles when in Sleep Mode. The minimum value is > 10 or the Cascade Group Size minus 2.
Input Toggle Rate
The average toggle rate of the data inputs (DIN) for both ports A and B.
Output Toggle Rate
The average toggle rate of the data outputs (DOUT) for both ports A and B.
Clock (MHz)
Clock frequency of the URAM or URAM module.

Following are values specified for both URAM ports A and B:

Data Width
Specify the exact data width if less than the maximum 72 bits.
Enable Rate
The percentage of time the URAM is enabled.
Write Enable
The percentage of time the write enable input is asserted, independently of the Enable Rate. The write enable pins are the URAM RDB_WR_A and RDB_WR_B pins.
Note: The following rule is applicable when you specify Enable Rate and Sleep Rate. For each of the ports A and B, the sum of (Enable Rate / Cascade Group Size) and Sleep Rate must not exceed 100%.