create_debug_port - 2021.2 English

A port can have one or more connection points to support one or more nets to debug. As a default new ports are defined as having a width of 1, allowing only one net to be attached. You can change the port width of probe ports to support multiple signals using the set_property port_width command (see Examples).

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.

-verbose - (Optional) Temporarily override any message limits and return all messages from this command.

<type> - (Required) The type of debug port to insert. The supported port types are:

• clk - Defines the clock port for connecting the ILA debug core to a clock domain. Each debug core can only have one clk port, and each clk port can only connect to one clock domain. Therefore you must use multiple ILA cores to probe signals from different clock domains.
  Important: Ensure that the connected clocks are free-running clocks. Failure to do so could result in an inability to communicate with the debug core when the design is loaded onto the device.
• probe - Provides probe points to connect to signals that are marked for debugging with the MARK_DEBUG property. The ILA debug core can contain multiple probe ports, which are automatically numbered by the Vivado tool when the port is added to the core. Each probe port can contain one or more channels, or connection points, as defined by the PORT_WIDTH property.
• trig_in/trig_in_ack, and trig_out/trig_out_ack - The ILA probe trigger comparators used to detect specific comparison conditions on the probe inputs to the ILA core. trig_in and trig_in_ack, and trig_out and trig_out_ack should be added to the debug core as port pairs when used. Refer to the Vivado Design Suite User Guide: Programming and Debugging (UG908) for more information.

The following example creates a new debug core, and then adds an additional probe port to the core, then sets the width of that new port to 8, and connects signals to the probe port:

create_debug_core myCore ila
create_debug_port myCore probe
set_property PORT_WIDTH 8 myCore/probe1
connect_debug_port -channel_start_index 1 myCore/probe1 \
{m1_cyc_i m1_ack_o m1_err_o m1_rty_o}