The Vivado tool lets you add different design sources including Verilog, VHDL, EDIF, NGC format cores, SDC, XDC, DCP design checkpoints, Tcl constraints files, and simulation test benches. These files can be sorted in a variety of ways using the tabs at the bottom of the Sources window (Hierarchy, Libraries, or Compile Order).
Important: NGC format files are not supported in the Vivado Design Suite for
UltraScale™
devices. It is
recommended that you regenerate the IP using the Vivado Design Suite
IP customization tools with native output products. Alternatively, you can use the
NGC2EDIF command to migrate the NGC file to EDIF format for importing. However, Xilinx recommends using native Vivado IP rather than
XST-generated NGC format files going forward.
The Vivado IDE includes a context sensitive text editor to create and develop RTL sources, constraints files, and Tcl scripts. You can also configure the Vivado IDE to use third party text editors. Refer to the Vivado Design Suite User Guide: Using the Vivado IDE (UG893) for information on configuring the Vivado tool.