High-Level Synthesis C-Based Design - 2021.2 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

Document ID
UG892
Release Date
2021-11-17
Version
2021.2 English

The C-based High-Level Synthesis (HLS) tools within the Vivado Design Suite enable you to describe various DSP functions in the design using C, C++, and SystemC. You create and validate the C code with the Vivado HLS tools. Use of higher-level languages allows you to abstract algorithmic descriptions, data type, specification, etc. You can create “what-if” scenarios using various parameters to optimize design performance and device area.

HLS lets you simulate the generated RTL directly from its design environment using C-based test benches and simulation. C-to-RTL synthesis transforms the C-based design into an RTL module that can be packaged and implemented as part of a larger RTL design, or instantiated into an IP integrator block design.

Video: For various training videos on Vivado HLS, see the Vivado High-Level Synthesis video tutorials available from the Vivado Design QuickTake Video Tutorials page on the Xilinx website.

The HLS tool flow and features are described in the following resources:

  • Vivado Design Suite User Guide: High-Level Synthesis (UG902)
  • Vivado Design Suite Tutorial: High-Level Synthesis (UG871)