The IP core includes, or requires, specific files to support the IP in the overall design flow. These include files such as a Verilog or VHDL instantiation template to facilitate integrating the IP module into your design, design constraints files (XDC) that are included to provide timing or physical constraints for the IP core, and synthesized netlists or design checkpoints to support the IP in the design hierarchy. Collectively these files are referred to as output products. Some of these files are included with the packaged IP in the Xilinx IP Catalog, and some are generated for the customized IP in the current design.
When an IP is customized from the IP Catalog, the Generate Output Products dialog box is opened. However, you can also open this dialog box at any time by right-clicking the IP in the Sources window and selecting the Generate Output Products command.
By default, synthesized design checkpoint (DCP) files are generated automatically for IP that supports the out-of-context flow. However, you can disable DCP file generation when creating output products by changing to Synthesis Options to Global synthesis. For more information, on the using the Out-of-Context flow see this link in the Vivado Design Suite User Guide: Designing with IP (UG896).
With the output products required by the IP core added to your design project, you must now instantiate the IP into your design hierarchy. This involves integrating the IP module or entity into the design as described in Instantiating IP Into the Design.