Memory IP 7 Series Support - 2021.2 English

Vivado Design Suite User Guide: System-Level Design Entry (UG895)

Document ID
UG895
Release Date
2021-11-10
Version
2021.2 English

Memory IP in Xilinx 7 series devices requires special handling. Board designers should test the Memory IP configuration on the board before adding the PRJ file into the board support area.