The Memory IP creates memory controllers for Xilinx devices and IP. Memory IP creates complete customized RTL source code, pinout, and design constraints for the selected FPGA, and script files for implementation and simulation.
In 7 series devices, memory IP is referred to as Memory Interface Generator (MIG). This terminology is deprecated with the UltraScale™ and UltraScale+ devices. See the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150), and Zynq-7000 SoC and 7 Series FPGAs Memory Interface Solutions (UG586) for more information.
For memory IP on the Zynq® UltraScale+™ MPSoC processor, the Vivado tools launch a pin planning project, and lets you set the appropriate pins for that device. See this link in the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).
The Designing with IP Design Hub in the Xilinx Document Navigator provides videos and links to Memory IP documentation.