Most Xilinx IP deliver RTL sources for a single language only, either Verilog or VHDL, effectively disabling simulation for language locked simulators if you do not have licensing for the language supported by the IP.
To simulate your design and include IP, the Vivado tools ensure the availability of an appropriate simulation model for the IP using the project property Simulator language setting. The
SIMULATOR_LANGUAGE property of the current project lets you tell the Vivado tool which language your simulator supports. The values are Verilog, VHDL, and Mixed. Set this property in Manage IP, Project-based, and Non-project based flows.
Some IP deliver simulation files for VHDL and some for Verilog. When the simulator language is set to Mixed, the same module for both languages can be sent to the simulator by different IP.
The Vivado simulator is a mixed language simulator and can handle simulation models in both VHDL and Verilog. If you are using a third-party simulator and have license for a single language only, change the Simulator language to match your license.
If the IP does not deliver a behavioral model or does not match the chosen and licensed simulator language, the Vivado tools automatically generate a structural simulation netlist (<ip_name>_sim_netlist.v or <ip_name>_sim_netlist.vhdl) to support simulation.
When you generate IP output products, enable the synthesized design checkpoint (DCP) option to ensure that the Vivado IDE can deliver a structural simulation netlist for the IP. For more information, see Generating Output Products.
To have all files required for simulation available in the IP <project_name>.gen directory for placement in a revision control system it is recommended you run synthesis first.
If your simulator language is not set to Mixed, then you might be required to generate the IP using the default OOC synthesis. If the IP you are using does not deliver RTL in the simulation language specified you must create an
_sim_netlist.v or an
_sim_netlist.vhdl file to simulate. These files are created as part of the OOC synthesis flow only. The following message displays when you have a mismatch between available simulation files and the Simulation Language setting.