Examining Generated Output Products - 2021.2 English

Vivado Design Suite User Guide : Designing with IP (UG896)

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2021.2 English

The IP Sources window shows the generated output products for all IP in the project. By default, the output products for an IP are written to the local project directory, at <project_name>.gen/sources_1/ip/<ip_name>; however, when you customize the IP from the IP catalog, the IP location can be specified as outside the local project directory.

After generating the synthesis output products, the Vivado IDE creates and launches a design run to produce the OOC DCP.

By default, the Vivado IDE creates a synthesized design checkpoint (DCP) file automatically during the generation process for most Vivado Design Suite IP.

When performing synthesis of the top-level design, IP is marked for the out-of-context flow with an associated DCP file, and treated as a black box because it is being synthesized OOC.

While the synthesis run is processing, the OOC related files are shown as missing.

If you elected to use Global Synthesis, and to not generate the DCP, the Vivado IDE does not create the structural simulation netlist and stub files.

If you do not generate output products, the instantiation templates are the only generated product (besides the XCI and BOM files, which are not displayed) shown in the following figure.

Figure 1. IP Customization with Generation of Output Products Skipped

As shown in the following figure, when the output products are generated, the IP Sources window lists unencrypted files.

Figure 2. IP Customization with Output Products Generated, Including OOC DCP

These files include: the instantiation templates, synthesis and simulation targets, XDC constraints, a change log, and other products.

By default, the Vivado IDE creates an OOC DCP along with structural simulation netlists (<ip_name>_sim_netlist.v or <ip_name>_sim_netlist.vhdl) and creates stub files (*_stub.v/*_stub.vhdl) for use with third-party synthesis tools to infer a black box for the IP.

Note: In versions of Vivado Design Suite that are older than 2015.3, the simulation files are named *_funcsim.v and *_funcsim.vhdl.
Note: Not all output products for an IP are shown in the IP Sources after generation. Encrypted files are not shown, nor are XDC files that are not placed in the synthesis file group. To see these files, look in the Design Sources or Compiler Order views. You can also use the report_compile_order command.