The Vivado tools create instantiation templates after IP customization, regardless of whether you generated the output products. The instantiation templates display in the
Sources > IP Sources > Instantiation Template directory.
After you create an IP customization, open the IP instantiation template and copy the relevant code from the template into your code. The Vivado tool generates both a VHDL and a Verilog instantiation template that you select from and copy and paste into your RTL design.
To use the instantiation template in your design, do the following steps:
- Open the instantiation template file for the IP customization by double-clicking the file in the Sources view, or by selecting the file using the Open Files command.
- Highlight the instantiation template between the comments as indicated in the text of the instantiation template, and copy the section.
- Open the design HDL file in which you want to instantiate the IP either at the top-level or in the hierarchy of the design.
- Paste the copied template to the location of your choice.
- Edit the HDL to integrate the template into your design as needed; for example, change the port connections, and give the instantiation a unique name.
After the IP is instantiated into a design, the IP is listed correctly in the design hierarchy. With the IP customization properly instantiated into your design, you are ready to synthesize the IP along with the rest of your design, either as a black box if the OOC flow is used, or with the top-level of the design, if you are using global synthesis. See Synthesis Options for IP for more details.