Xilinx devices can optionally use an internally generated reference voltage by enabling the INTERNAL_VREF constraint. Internal generation removes the need to provide for a particular VREF supply rail on the PCB and frees the multipurpose VREF pins in a given I/O bank to be used as normal I/O pins.
Tip: All I/O banks that do not have an INTERNAL_VREF constraint are shown under the NONE folder in the Device Constraints window.
To create an INTERNAL_VREF constraint, drag and drop the I/O bank onto the desired voltage folder (for example, 0.7V or 0.84V) in the Device Constraints window.
Figure 1. Creating an Internal VREF Constraint