To create design for hard block planning, complete the following steps
- 1. Create a project that targets a Versal ACAP device. In this lab we will be
creating a PCIE design that targets xcvc1902-vsvd1760-1LP-i-L. Ensure that the
"Do not specify sources at this time" option is
checked while creating an RTL project.
- Once the project loads, click on the + button in the
BD canvas to add
Versal ACAP Integrated Block for PCI Express
- After adding the IP onto the BD canvas, click the Run Block
Automation ribbon that appears above the BD canvas.
- Running the block automation instantiates a pcie_versal_0_support block. This
block contains the GT module that the PCIE requires to talk to the external
- Once the block automation completes, click the Generate Block
Design option under IP
Integrator menu of the Flow
Navigator window. When a subsequent prompt appears,
leave the settings at default and click the Generate
- Create a top-level HDL wrapper before synthesizing the
- The next step is to synthesize the design and open the synthesized design.
Hard IP option in
Windows menu appears only once you
open synthesized design.
- Once you open a synthesized design, it reads and processes netlist objects
and collects all hard-IPs available in a design. This planner allows you to
cross-probe the location in device window view for changing or assigning the
- In our current design, we have 2 hard-IPs (PCI Express and GTY_QUAD) whose
location can be planned using the Hard Block Planner tool. You can do so by
selecting the drop-down menu under the Site column and picking a suitable site
from the list.Note: The site for the PCI Express hard IP is pre-determined by the PCIE Express IP in IPI.