The Vivado Design Suite provides simulation models as a set of files and libraries. Your simulation tool must compile these files prior to design simulation. The simulation libraries contain the device and IP behavioral and timing models. The compiled libraries can be used by multiple design projects.
During the compilation process, Vivado creates a default
initialization file that the simulator uses to reference the compiled libraries. The
compile_simlib command creates the file in the
library output directory specified during library compilation. The default
initialization file contains control variables that specify reference library paths,
optimization, compiler, and simulator settings. If the correct initialization file is
not found in the path, you cannot run simulation on designs that include Xilinx primitives.
The name of the initialization file varies depending on the simulator you are using, as follows:
- Questa Advanced Simulator/ModelSim: modelsim.ini
- Xcelium: cds.lib
- VCS: synopsys_sim.setup
- Riviera/Active-HDL: library.cfg
For more information on the simulator-specific compiled library file, see the third-party simulation tool documentation.
You can compile libraries using the Vivado IDE or using Tcl commands, as described in the following sections.