Managing Message Output - 2021.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2021-10-22
Version
2021.2 English

If your HDL design produces a large number of messages (for example, via the $display Verilog system task or report VHDL statement), you can limit the amount of text output sent to the Tcl Console and log file. This saves computer memory and disk space. To accomplish this, use the -maxlogsize command line option:

  1. In the Flow Navigator, right-click on SIMULATION and select Simulation Settings.
  2. In the Settings dialog box, add -maxlogsize <size> next to xsim.simulate.xsim.more_options, where <size> is the maximum amount of text output in megabytes.