Use the SECUREIP library for functional and timing simulation of complex device components, such as GT.
Xilinx leverages the encryption methodology as specified in the IEEE standard Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP) (IEEE-STD-P1735). The library compilation process automatically handles encryption.
The following table lists special considerations that must be arranged with your simulator vendor for using these libraries.
|Siemens EDA ModelSim SE||Siemens||If design entry is in VHDL, a mixed language license or a SECUREIP OP is required. Contact the vendor for more information.|
|Siemens EDA Questa Advanced Simulator|
|Active-HDL||Aldec||If design entry is VHDL, a mixed language license is required.|
VHDL SECUREIP Library
The UNISIM library contains the wrappers for VHDL SECUREIP. Place the following two lines at the beginning of each file so that the simulator can bind to the entity:
Library UNISIM; UNISIM.VCOMPONENTS.all;
Verilog SECUREIP Library
When running a simulation using Verilog code, you must reference the SECUREIP library for most simulators.
If you use the precompiled libraries, use the correct directive to point to the precompiled libraries. The following is an example for the Vivado simulator:
-fswitch. The file list is available in the following path: <Vivado_Install_Dir>/data/secureip/secureip_cell.list.f.