Verilog Language Support Exceptions - 2021.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2021-10-22
Version
2021.2 English

The following table lists the exceptions to supported Verilog language support.

Table 1. Verilog Language Support Exceptions
Verilog Construct Exception
Compiler Directive Constructs
`unconnected_drive not supported
`nounconnected_drive not supported
Attributes
attribute_instance not supported
attr_spec not supported
attr_name not supported
Primitive Gate and Switch Types
cmos_switchtype not supported
mos_switchtype not supported
pass_en_switchtype not supported
Generated Instantiation
generated_instantiation

The module_or_generate_item alternative is not supported.

Production from IEEE standard (see IEEE Standard Verilog Hardware Description Language (IEEE-STD-1364-2001) section 13.2 ):

generate_item_or_null ::= 
generate_conditonal_statement |
generate_case_statement |
generate_loop_statement |
generate_block |
module_or_generate_item

Production supported by Simulator:

generate_item_or_null ::=
generate_conditional_statement|
generate_case_statement |
generate_loop_statement |
generate_blockgenerate_condition
genvar_assignment

Partially supported.

All generate blocks must be named.

Production from standard (see IEEE Standard Verilog Hardware Description Language (IEEE-STD-1364-2001) section 13.2):

generate_block ::=
begin
[ : generate_block_identifier ]
{ generate_item }
end

Production supported by Simulator:

generate_block ::=
begin:
generate_block_identifier {
generate_item }
end
Source Text Constructs
Library Source Text
library_text not supported
library_descriptions not supported
library_declaration not supported
include_statement This refers to include statements within library map files (See IEEE Standard Verilog Hardware Description Language (IEEE-STD-1364-2001) section 13.2. This does not refer to the `include compiler directive.
System Timing Check Commands
$skew_timing_check not supported
$timeskew_timing_check not supported
$fullskew_timing_check not supported
$nochange_timing_check not supported
System Timing Check Command Argument
checktime_condition not supported
PLA Modeling Tasks
$async$nand$array not supported
$async$nor$array not supported
$async$or$array not supported
$sync$and$array not supported
$sync$nand$array not supported
$sync$nor$array not supported
$sync$or$array not supported
$async$and$plane not supported
$async$nand$plane not supported
$async$nor$plane not supported
$async$or$plane not supported
$sync$and$plane not supported
$sync$nand$plane not supported
$sync$nor$plane not supported
$sync$or$plane not supported
Value Change Dump (VCD) Files

$dumpportson

$dumpports

$dumpportsoff

$dumpportsflush

$dumpportslimit

$vcdplus

not supported