The Vivado Integrated Design Environment (IDE) supports the following languages:
- VHDL, see EEE Standard VHDL Language Reference Manual (IEEE-STD-1076-1993)
- Verilog, see IEEE Standard Verilog Hardware Description Language (IEEE-STD-1364-2001)
- SystemVerilog Synthesizable subset. See IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language (IEEE-STD-1800-2009)
- IEEE P1735 encryption, see Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP) (IEEE-STD-P1735)
This appendix lists the application of Mixed Language in the Vivado simulator, and the exceptions to Verilog, SystemVerilog, and VHDL support.