In digital designs, clocks represent the time reference for reliably transferring data from register to register. The Xilinx® Vivado® Integrated Design Environment (IDE) timing engine uses the clock characteristics to compute timing path requirements and report the design timing margin by means of the slack computation.
For more information, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
Clocks must be properly defined in order to get the maximum timing path coverage with the best accuracy. The following characteristics define a clock:
- It is defined on the driver pin or port of its tree root, which is called the source point.
- Its edges are described by the combination of the period and the waveform properties.
- The period is specified in nanoseconds. It corresponds to the time over which the waveform repeats.
- The waveform is the list of rising edge and falling edge absolute times, in nanoseconds, within the clock period. The list must contain an even number of values. The first value always corresponds to the first rising edge. Unless specified otherwise, the duty cycle defaults to 50% and the phase shift to 0 ns.
As shown in the following figure, the clock Clk0 has a 10 ns period, a
50% duty cycle and 0 ns phase. The clock Clk1 has 8 ns period, 75% duty
cycle (high time is 6 ns out of 8 ns) and a 2 ns rising edge phase shift.
Clk0: period = 10, waveform = {0 5}
Clk1: period = 8, waveform = {2 8}
