Multi-Bit Register Names - 2021.2 English

By default, the register name is based on the signal name in the RTL, plus the _reg suffix. You can only query and constrain individual bits of the multi-bit register in your XDC commands.

For example, for a signal defined as follows in VHDL and Verilog, the instance names generated during the elaboration are loadState_reg[0], loadState_reg[1], and loadState_reg[2]:

VHDL: signal loadState: std_logic_vector(2 downto 0); Verilog: reg [2:0] loadState;

The following figure shows the schematic of the register. The multi-bit register appears as a vector of single-bit registers. The vector is represented in a compact way whenever possible in the schematics. Each individual bit can also be displayed separately.

Figure 1. Multi-Bit Register in Elaborated Design

You can only constrain each register individually or as a group by using the following patterns:

• Register bit 0 only

  loadState_reg[0]

• All register bits

  loadState_reg[*]

Because the names above also correspond to the names in the post-synthesis netlist, any constraint based on them will most probably work for implementation as well.