When the Timing Constraints wizard is open, it prevents most actions in the Vivado IDE, including using the Tcl Console or running timing analysis, in order to avoid database discrepancies. The wizard window is always in front of the other Vivado IDE windows. If you need to access the Vivado IDE menus or windows, you must move the wizard window to the side.
Only the following features are available while the Timing Constraints wizard is open:
- Reporting and visualizing the clock networks
- Most pages of the wizard have buttons to generate and access the clock network report in
order to visualize the clock topologies, their source point, and the shared
segments for some of the clocks.
Refer to the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906) for more details about the clock network report.
- Searching a name in source files or an object in the design in memory
- The Find and Find In Files dialog boxes are available from the Edit menu. You can use these dialog boxes to retrieve some information about the design while entering the constraints in the wizard.
- Creating and Viewing schematics
- You can select design objects in the main Vivado IDE window
and visualize them in schematics. All schematics features are available. Only
the last step of the Timing Constraints wizard, Asynchronous Clock Domain
Crossings, supports convenient schematics cross-probing when selecting one or
several entries in the Timing Paths tab.
Refer to the Vivado Design Suite User Guide: Using the Vivado IDE (UG893) for more info on using schematics.
- Visualizing constraints in memory with the Timing Constraints window
- Each page of the wizard includes a tab that shows the existing constraints of the same type as recommended by the step. This is convenient for quickly reviewing the details of constraints already created in the XDC files. For a complete view of all timing constraints in memory, the Timing Constraints window shows the full sequence of constraints, organized by XDC file, including scoping information. It also displays the invalid constraints.