The Xilinx® Vivado® Design Suite enables implementation of the following Xilinx device architectures: Versal® adaptive compute acceleration platform (ACAP), UltraScale™ , UltraScale+™ , and Xilinx 7 series FPGA. A variety of design sources are supported, including:
- RTL designs
- Netlist designs
- IP-centric design flows
jmo1616479964493.html#jmo1616479964493__image_ok3_lfn_3pb shows the Vivado tools flow.
Vivado implementation includes all steps necessary to place and route the netlist onto device resources, within the logical, physical, and timing constraints of the design.
For more information about the design flows supported by the Vivado tools, see the Vivado Design Suite User Guide: Design Flows Overview (UG892).