After design rule checking, the Vivado placer places clock and I/O cells before placing other logic cells. Clock and I/O cells are placed concurrently because they are often related through complex placement rules specific to the targeted Xilinx device. For UltraScale, UltraScale+, and Versal devices, the placer also assigns clock tracks and pre-routes the clocks. Register cells with IOB properties are processed during this phase to determine which registers with an IOB value of TRUE should be mapped to I/O logic sites. If the placer fails to honor an IOB property of TRUE, a critical warning is issued.
The placer targets at this stage of placement are:
- I/O ports and their related logic
- Global clock buffers
- Clock management tiles (MMCMs and PLLs)
- Gigabit Transceiver (GT) cells
Placing Unfixed Logic
When placing unfixed logic during this stage of placement, the placer adheres to physical constraints, such as LOC properties and Pblock assignments. It also validates existing LOC constraints against the netlist connectivity and device sites. Certain IP (such as Memory IP and GTs) are generated with device-specific placement constraints.
Clock Resources Placement Rules
Clock resources must follow the placement rules described in the 7 Series FPGAs Clocking Resources User Guide (UG472), UltraScale Architecture Clocking Resources User Guide (UG572) and Versal ACAP Clocking Resources Architecture Manual (AM003). For example, an input that drives a global clock buffer must be located at a clock-capable I/O site, must be located in the same upper or lower half of the device for 7 series devices, and in the same clock region for UltraScale devices. These clock placement rules are also validated against the logical netlist connectivity and device sites.
When Clock and I/O Placement Fails
If the Vivado placer fails to find a solution for the clock and I/O placement, the placer reports the placement rules that were violated, and briefly describes the affected cells.
Placement can fail because of several reasons, including:
- Clock tree issues caused by conflicting constraints
- Clock tree issues that are too complex for the placer to resolve
- RAM and DSP block placement conflicts with other constraints, such as Pblocks
- Over-utilization of resources
- I/O bank requirements and rules
In some cases, the Vivado placer provisionally places cells at sites, and attempts to place other cells as it tries to solve the placement problem. The provisional placements often pinpoint the source of clock and I/O placement failure. Manually placing a cell that failed provisional placement might help placement converge.
place_portsto run the clock and I/O placement step first. Then run
place_design. If port placement fails, the placement is saved to memory to allow failure analysis. For more information, run
place_ports -helpfrom the Vivado Tcl command prompt.
For more information about UltraScale clock tree placement and routing, see the UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949).