The Vivado Design Suite implementation process transforms a logical netlist and constraints into a placed and routed design, ready for bitstream generation. The implementation process walks through the following sub-processes:
- Opt Design: Optimizes the logical design to make it easier to fit onto the target Xilinx device.
- Power Opt Design (optional): Optimizes design elements to reduce the power demands of the target Xilinx device.
- Place Design: Places the design onto the target Xilinx device and performs fanout replication to improve timing.
- Post-Place Power Opt Design (optional): Additional optimization to reduce power after placement.
- Post-Place Phys Opt Design (optional): Optimizes logic and placement using estimated timing based on placement. Includes replication of high fanout drivers.
- Route Design: Routes the design onto the target Xilinx device.
- Post-Route Phys Opt Design (optional): Optimizes logic, placement, and routing using actual routed delays.
- Write Bitstream: Generates a bitstream for Xilinx device configuration. Typically, bitstream generation follows implementation.
For more information about writing the bitstream, see this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908).
Note: The Vivado Design Suite supports Module Analysis, which is the implementation of a part of a design to estimate performance. I/O buffer insertion is skipped for this flow to prevent over-utilization of I/O. For more information, search for “module analysis” in the Vivado Design Suite User Guide: Hierarchical Design (UG905).