The synchronization of an asynchronous reset is shown in the following figure for CLEAR-based synchronization, and in the subsequent figure for PRESET-based synchronization. The FF1 cell is respectively connected to the synchronized clear or preset signals and their deassertion can safely be timed against
clk_a. Note that flip-flops with
PRESET cannot be mixed within an asynchronous reset synchronizer.
The general recommendation is to avoid multiple synchronizations of the reset signal inside the destination clock domain. This means that there should not be any fanout of the reset from the source clock domain into the destination clock domain. This recommendation prevents the destination clock domain to come out of reset at different time which could put the design in an unknown state. Failing to follow this recommendation results in a critical CDC-11 Fan-out from launch flop to destination clock violation.
However, there are scenarios involving the FIFO Generator IP where it is safe to have multiple synchronizations of the reset signal inside the destination clock domain. The FIFO Generator enters the reset state asynchronously and comes out synchronously. It applies true synchronous reset to block RAM though the FIFO receives the asynchronous reset. There will not be a situation where some part of logic is out of reset and some part is still in reset as long as its
wr_rst_busy signal is used by the design to hold the data flow.
The AXI interface uses 5 FIFO Generator IPs to synchronize the reset in each of the destination clock domains and is another example of a reset circuitry that is safe by construction. In those scenarios when it is safe to synchronize the reset signal multiple times, the CDC-11 violations can be ignored.
The following figure illustrates an example of safe reset synchronization involving two FIFO Generators in the same destination clock domain.