- Timing Analysis: The Path Type and Requirement detail the timing analysis type (SETUP or HOLD) along with the timing path requirement. The Slack indicates whether or not the timing path requirement is met based on the timing analysis as dictated by the timing constraints. The Timing Exception indicates if any timing exceptions such as multicycle path or max delay have been applied to the timing path.
Checking the path requirement is often the first step in debugging missing or incorrect timing constraints:
- Paths with setup requirement under 4 ns must be reviewed to verify their validity in the design, especially for clock domain crossing paths.
- Paths with setup requirement under 2 ns are difficult to meet and must be avoided in general, especially for the older architectures.
- In general, when small setup requirements are present, check for missing timing exception constraints and also check the source and destination clock edges. The timing analysis always assumes the smallest positive difference between source and destination clock edges unless overridden by a timing exception constraint.
- Positive hold path requirements need to be reviewed as they are not common and are difficult to meet. When positive hold path requirements are present, check for missing multicycle path constraints for hold analysis that might have only been applied to the path for setup analysis. Also check the relationship between source and destination clocks for correctness.
- Datapath: The Path Delay, Logic Delay, and Net Delay detail the total datapath delay along with its breakdown into delay contribution by logic cells and nets.
Important: The LUT input pins have different delay characteristics. The physical pins (or site pins) of higher index are faster than the pins of lower index. Be aware of the difference in 7 series and UltraScale device LUT delay reporting. In 7 Series devices, the variable portion of LUT delay is reported as part of the net delay in front of the LUT. In UltraScale devices, the variable portion of LUT delay is reported as logic delay. Therefore, the 7 Series device
- If the Logic Delay makes up an unusually high proportion of the total datapath delay, for example 50% or higher, it is advised to examine the datapath logic depth and types of cells on the logic path, and possibly modify the RTL or synthesis options to reduce the path depth or use cells with faster delays.
- If the Net Delay dominates the total path delay for a setup path where the Requirement is reasonable, it is advised to analyze some of the physical characteristics and property characteristics of the path listed in this section. Specific items to look at include the High Fanout and Cumulative Fanout characteristics to understand if some nets of the path have a high fanout that could potentially be causing a placement problem. Also check the Hold Fix Detour characteristic to understand if hold fixing has occurred on the path.
Net Delay/Logic Delayratio will be larger than the ratio for UltraScale devices.
- Clocks: The Start Point Clock, End Point Clock, Clock Relationship, and Clock
Skew detail information regarding the timing path clocks. The Start Point Clock and
Endpoint Clock list the respective source clock and destination clock for the timing
Note: Almost all of the Timing Characteristics provided by
- Check that the Clock Relationship is correct and expected. For intra-clock paths or synchronous clock domain crossing paths, the relationship is labeled as "Safely Timed." You must verify that the Requirement and Clock Skew are reasonable. For asynchronous clocks, the relationship is labeled as "No Common Primary Clock", "No Common Period", "No Common Node", or "No Common Phase". Asynchronous clock domain crossing paths must be covered by timing exceptions (check the Timing Exception value).
- Check that the Clock Skew is reasonable. When analyzing clock skew, check the clock tree structure for cascaded clock buffers. In 7 series devices, check for different clock buffer types for the source and destination clocks. In UltraScale devices, it might be necessary to examine the placement and routing of the clock nets because it depends on logic loads placement. The crossing of a Clock Region boundary or an I/O Column can result in higher clock skew; this is expected.
report_design_analysisare available in a timing report.