Check Timing Section - 2021.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2021.2 English

The Check Timing section of the Timing Summary Report contains information about missing timing constraints or paths with constraints issues that need to be reviewed. For complete timing signoff, all path endpoints must be constrained.

For more information on constraints definition, see the Vivado Design Suite User Guide: Using Constraints (UG903).

Figure 1. Timing Summary Report: Check Timing Section

To generate Check Timing as a standalone report, do one of the following:

  • Run the Reports > Timing > Check Timing menu command.
  • Run the Tcl check_timing command.

When run from the Tcl console, the check_timing report can be scoped to one or more hierarchical cells using the -cells option. This option is not available from the Check Timing GUI. Note that the categories loops and latch_loops are not scoped in the Vivado Design Suite 2018.1.

The list of checks reported by default, as shown in the previous figure is:

  • pulse_width_clock: Reports clock pins that have only a pulse width check associated with the pin, and no setup or hold check, no recovery, removal, or clk > Q check.
  • no_input_delay: Number of non-clock input ports without any input delay constraints.
  • no_clock: Number of clock pins not reached by a defined timing clock. Constant clock pins are also reported.
  • constant_clock: Checks for clock signals connected to a constant signal (gnd/vss/data).
  • unconstrained_internal_endpoints: Number of path endpoints (excluding output ports) without a timing requirement. This number is directly related to missing clock definitions, which is also reported by the no_clock check.
  • no_output_delay: Number of non-clock output ports without at least one output delay constraint.
  • multiple_clock: Number of clock pins reached by more than one timing clock. This can happen if there is a clock multiplexer in one of the clock trees. The clocks that share the same clock tree are timed together by default, which does not represent a realistic timing situation. Only one clock can be present on a clock tree at any given time.

    If you do not believe that the clock tree is supposed to have a MUX, review the clock tree to understand how and why multiple clocks are reaching the specific clock pins.

  • generated_clocks: Number of generated clocks that refer to a master clock source which is not part of the same clock tree. This situation can occur when a timing arc is disabled on the logical path between the master clock and the generated clock source points. This check also applies to individual edges of the generated clocks when specified with the -edges option: the logical path unateness (inverting/non-inverting) must match the edge associations between the master and generated clocks.
  • loops: Number of combinational loops found in the design. The loops are automatically broken by the Vivado IDE timing engine to report timing.
  • partial_input_delay: Number of non-clock input ports with only a min input delay or max input delay constraint. These ports are not reported by both setup and hold analysis.
  • partial_output_delay: Number of non-clock output ports with only a min output delay or max output delay constraint. These ports are not reported by both setup and hold analysis.
  • latch_loops: Checks for and warns of loops passing through latches in the design. These loops will not be reported as part of combinational loops, and will affect latch time borrowing computation on the same paths.