Another way to review design placement is to analyze cell placement. The Highlight Leaf Cells command helps in this analysis.
- In the Netlist Window, select the levels of hierarchy to analyze.
- From the popup menu, select .
- If you select multiple levels of hierarchy, select Cycle Colors.
The leaf cells that make up the hierarchical cells are color coded in the Device window.
The color coding shows the placement of the key hierarchical blocks in the device. The
usbEngine0 (in blue):
- Uses a number of Block RAM and DSP48 cells.
- Is in the middle clock regions of the chip.
- Is intermingled with other logic (
fftEngine) in the design.
It is easy to see that the
fftEngine (in green) and the
cpuEngine (in yellow) are intermingled. The two blocks primarily use different resources (DSP48 as opposed to slices). Intermingling makes best use of the device.