High fanout nets often lead to implementation issues. As die sizes increase with each FPGA family, fanout problems also increase. It is often difficult to meet timing on nets that have many thousands of endpoints, especially if there is additional logic on the paths, or if they are driven from non-sequential cells, such as LUTs or distributed RAMs.
Many times, designers address the high fanout nets in RTL or synthesis by using a global fanout limit or a
MAX_FANOUT attribute on a specific net. Physical optimization (
phys_opt_design) automatically replicates the high fanout net drivers based on slack and placement information, and usually significantly improves timing. Xilinx recommends that you drive high fanout nets with a fabric register (FD*), which is easier to replicate and relocate during physical optimization. It is important to look at the list of high fanout signals post synthesis as well as post physical optimization. The command to identify these nets is
Once the report has been generated, the timing through the high fanout nets and corresponding schematic can be reviewed. This report does not list clocks as the high fanout driver. If a BUFG is in the Driver Type column, this BUFG is driving logic and possibly also clock pins.
### Report the high fanout net report_high_fanout_nets -load_types -max_nets 100 ### Report timing through specific high fanout net report_timing -through [get_nets I_GLOBAL_RST_N_i] -name high_fanout_1
Following is an example of a design in which
phys_opt_design was able to reduce the fanout:
Post Place Checkpoint:
-load_typesoption with the
report_high_fanout_netscommand also shows the delay and the various types of loads for the high-fanout nets.
The Timing Report for that net post physical optimization is:
The fanout on that particular net was reduced from 2945 down to 464. More importantly, the reduction in fanout improved the timing (on this particular path the improvement was over 1 ns).
The FLAT_PIN_COUNT property of each net indicates the number of leaf cells connected to this net throughout the design hierarchy. Use the
get_property command to extract the FLAT_PIN_COUNT property:
get_property FLAT_PIN_COUNT [get_nets my_hfn]