Identifying the Longest Logic Delay Paths in the Design - 2021.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2021.2 English

Timing paths correspond to logical paths in the design.Their delay is the accumulation of cell delays and net delays. The Vivado® synthesis and implementation tools are timing-driven and work on optimizing the worst violating paths of your design throughout the compilation flow. If accumulated cell delay for a path is equal to or higher than the timing requirement (for example, usually the clock period of the path), the design is unlikely to meet timing after implementation. Analyzing the logic delay is better than simply counting logic levels, because it shows what the worst paths are before estimated or routed net delays become a factor. The result of this analysis is a list of the worst timing paths before placement and routing, and without net delay.

It is important to identify the paths that are the worst in terms of timing and not necessarily levels of logic. For example, unregistered block RAM have very large clock to out delay, while a series of carry chains may have multiple levels of levels of logic, each with a small delay. You must analyze these paths carefully before implementation. There are three typical categories for these long delay paths:

  • Block RAMs that do not take advantage of the embedded output register
  • DSP Slices that are not pipelined
  • Long logic paths

The most efficient method of identifying these long paths is to run a timing report post synthesis with the routing estimates set to none. This can be done by changing the Interconnect model to none in the Timer Settings tab of the Vivado IDE Timing Report dialog box, or by using the following Tcl command in the Tcl console or shell:

set_delay_model -interconnect none

Review the timing results to identify any failing paths. If there are paths that fail to meet timing without any routing delay, these paths will be impossible to meet timing with actual routing. These paths must be addressed immediately. Typically, these would have to be fixed in RTL, but the violations could also be due to missing synthesis attributes, or incorrect timing constraints. After implementing the changes, the design will have sufficient slack as shown in the following figure.

Figure 1. Timing Report with 0 Interconnect