You can select the interconnect model to be used in your analysis of timing paths:
- actual: provides the most accurate delays for a routed design.
- estimated: includes an estimate of the interconnect delays based on the placement and connectivity of the design onto the device prior to implementation. Estimated delay can be specified even if the design is fully routed.
- none: includes no interconnect delay in the timing analysis; only the logic delay
Equivalent Tcl command:
set_delay_model -interconnect <arg>
For more information about
refer to the
Design Suite Tcl Command Reference Guide (UG835).