LUTRAM Read/Write Potential Collision - 2021.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2021.2 English

In the LUTRAM Read/Write Potential Collision example below, the data is written inside the LUTRAM with the write clock and the output of the LUTRAM is captured by the read clock. When the read and write addresses are different, there is no CDC path between the write and the read clocks. However, when the write and read addresses are the same, then there is a CDC path between the write clock and the read clock.

To avoid a CDC path between the write and read clocks, it is necessary to ensure that the logic around the LUTRAM can never generate the same read and write addresses during active read and write operations. When this condition is ensured, the CDC violation related to this topology can be waived. Xilinx's FIFO Generator IP, for example, has a built-in logic that prevents any read/write collision.

Figure 1. LUTRAM Read/Write Potential Collision