The Pulse Width area of the Design Timing Summary section displays all checks related to pin switching limits:
- Min low pulse width
- Min high pulse width
- Min period
- Max period
- Max skew (between two clock pins of a same leaf cell, such as for PCIe or GT [UltraScale devices only]).
The reported values are:
- Worst Pulse Width Slack (WPWS): Corresponds to the worst slack of all the timing checks listed above when using both min and max delays.
- Total Pulse Width Slack (TPWS): The sum of all WPWS violations, when considering only the worst violation of each pin in the design. Its value is:
- 0 ns when all related constraints are met.
- Negative when there are some violations.
- Number of Failing Endpoints: The total number of pins with a violation (WPWS< 0 ns).
- Total Number of Endpoints: The total number of endpoints analyzed.