Report Clock Networks - 2021.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2021-10-27
Version
2021.2 English

The Report Clock Network command can be run from:

  • The Flow Navigator in the Vivado┬« IDE, or
  • The Tcl command:
    report_clock_networks -name {network_1}

Report Clock Networks provides a tree view of the clock trees in the design. See the following figure. Each clock tree shows the clock network from source to endpoint with the endpoints sorted by type.

Figure 1. Clock Networks

The clock trees:

  • Show clocks defined by the user or generated automatically by the tool.
  • Report clocks from I/O port to load.
    Note: The full clock tree is only detailed in the GUI form of the report. The text version of this report shows only the name of the clock roots.
  • Can be used to find BUFGs driving other BUFGs.
  • Shows clocks driving non-clock loads.

There is a folder containing each primary clock and any generated clocks defined in the design. A separate folder displays each unconstrained clock root.

Use the filter Ports, Nets, Instances, and related buttons to reduce the amount of data displayed in the clock tree. The filter options can be viewed by clicking on the icon.

Figure 2. Clock Networks Filter

To view a schematic of the clock path:

  1. Select an object in the tree.
  2. Run the Trace to Source popup command.